Generative AI for Algorithm to Silicon Mapping

Generative AI for Algorithm to Silicon Mapping

Classes on Weekend

Duration : One Semester (4 Months)  

by Dr. Shoab Ahmed Khan Chancellor SS-CASE-IT and CEO CARE Pvt Ltd.

Generative AI for Algorithm to Silicon Mapping

 

Our course on Algorithm to Silicon is meticulously crafted to equip you with foundation skills in Generative AI, algorithm development, architecture design, RTL coding, Design Verification, mapping on FPGAs and ASICs and more. Delve into the intricacies of digital system design, our focus shall be to consider computationally intensive algorithms, that otherwise are written in programming languages to run on general-purpose-computers or GPUs. We shall learn mapping these algorithms in Silicon. These can then be mapped on FPGAs or custom ASICs. The course shall also teach you the art of Chip Designing.

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Course Educational Objective

1. To jump start a career in digital system design and design verification by fully mastering code generation techniques using Gen AI and understanding strategies for mapping complex algorithms in HW.
2. To create ideas for innovation driven startups in digital design
3.  To be a master trainer to become part of National ambition of making Pakistan a destination in Fabless Semiconductor Design Services

Course Duration

One semester (4 Months)

Pre-Requisite

An undergraduate degree in EE, CE, MTS, SE, CS, AI, DS, or Cyber Sec is recommended, with preference given to students who have completed basic courses in Logic Design, Computer Organization, and Programming.

We shall be generating all the code for the assignments and projects in Python, Verilog and System Verilog using Gen AI tools.

Mode of Learning

Online and on campus classes

For Any Query please contact at :

Ms. Laiba Tanveer ( 0331-111-7956)

Grading

Three categories of registration

1. Credit Hours and Certificate Mentioning Grade in the course (Class participation, submission of all assignment, projects, taking all exams)
2. Certification of Participation (Class participation, submission of all assignments)
3. Certification of Attendance (Class participation and submission of assignments is optional)

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Book

1. Material from internet & research papers
2. Shoab Khan, Digital Design for Signal Processing Systems. John Wiley & Sons

• Module-1

  1. 1. Algorithm to Silicon Mapping (8-weeks)

     • Digital Design Flow – Overview and Challenges
     • Algorithms
       • Data Structure Algorithm
       • DSP Algorithm
       • Machine Learning
       • Deep Learning (CNN)
     • SystemVerilog
       • RTL Design
       • Functional Verification
     • Arithmetic
       • Fixed-point & Floating-point
       • Canonic Forms
     • Basic Computational Units
       • Addition, Multiplication, Multiply Accumulate MAC, Arithmetic and Logic Shifting
       • Sine and Cosine Generation
       • Other mathematical functions
     • Architecture Design
       • Fully Parallel
       • Systolic
       • Time Shared
       • Micro-coded State machines

• Module-2

  1. 1. Module 2 has 7 Different Streams (6 weeks)

        • Architecture Design (Dr Mohsin)
        • Overview of computer architecture
        • Instruction set architecture (ISA)
        • Microarchitecture design: pipelining, superscalar, out-of-order execution
        • Front-End Design (RTL Level) (Dr Sheikh M Farhan/Dr Shoab Khan)
        • Detailed RTL design using Verilog
        • Advanced constructs and coding styles
        • Design projects: implementing complex digital systems
        • Functional Verification (Dr Zaheer)
        • Verification methodologies: directed testing, random testing, coverage-driven verification
        • SystemVerilog and UVM (Universal Verification Methodology)
        • Creating effective testbenches and verification environments
        • Synthesis and Timing Analysis (Dr Shafaat Bazaz)
        • Synthesis tools and techniques: RTL to gate-level netlist
        • Constraints and optimization: timing, area, power
        • Static timing analysis (STA): setup/hold time analysis, clock tree synthesis
        • Physical Design (Layout) (Dr Shafaat Bazaz)
        • Layout design: placement, routing, and compaction
        • Design rules and constraints: DRC, LVS
        • Tools and methodologies: EDA tools for physical design
        • Embedded Software and Drivers (Dr Saeed)
        • Programming languages: C, C++
        • Real-time operating systems (RTOS): basics and applications
        • Software development tools: IDEs, compilers, debuggers
        • Basics of device drivers: role and functionality
        • Writing drivers for common peripherals (e.g., sensors, communication modules)
        • Firmware development: bootloaders, system initialization

        • Tools used

          l  Python

          l  Verilog / System Verilog

          l  FPGA Logic Synthesis

          l  Cadence Tools XCELIUM2003

• Course Learning Outcomes (CLO)

  1. Fundamental Understanding:
     • CLO1: Demonstrate a comprehensive understanding of the digital design flow, including the challenges and techniques involved in mapping algorithms to silicon.
  2. Algorithm Design and HW Mapping:
     • CLO2: Generate using GenAI code for realizing data structure algorithms, DSP algorithms, and machine learning algorithms (including CNNs) for efficient mapping in hardware.
  3. Hardware Description Languages:
     • CLO3: Apply Verilog and SystemVerilog for RTL design and functional verification, demonstrating proficiency in generating code using Gen AI
  4. Arithmetic and Computational Units:
     • CLO4: Generate code to implement basic arithmetic operations and computational units (e.g., addition, multiplication, MAC, trigonometric functions) in hardware.
  5. Architecture Design:
     • CLO5: Design and evaluate different digital architectures (e.g., fully parallel, systolic, time-shared, micro-coded state machines) for specific computational tasks.
  6. Practical Tool Usage:
     • CLO11: Utilize industry-standard tools such as Python, Verilog/SystemVerilog, FPGA logic synthesis tools, and Cadence tools (XCELIUM2003) for digital design and verification tasks.
  7. Project Management and Collaboration:
     • CLO12: Work collaboratively on design projects, demonstrating project management skills and the ability to integrate and apply interdisciplinary knowledge.
  8. Steam 1: Advanced Digital System Design:
     • CLO6: Create detailed RTL designs using advanced constructs and coding styles, implementing complex digital systems effectively.
  9. Steam 2: Verification Techniques:
     • CLO7: Employ verification methodologies, including directed testing, random testing, and coverage-driven verification, using SystemVerilog and UVM.
  10. Stream 3: Synthesis and Timing Analysis:
      • CLO8: Perform synthesis and timing analysis, optimizing designs for timing, area, and power, and conduct static timing analysis (STA).
  11. Steam 4: Physical Design and Layout:
      • CLO9: Execute physical design tasks, including placement, routing, and compaction, adhering to design rules and constraints (DRC, LVS).
  12. Stream 5: Embedded Systems Programming:
      • CLO10: Develop embedded software and drivers using programming languages (C, C++), real-time operating systems (RTOS), and firmware development tools.
  13. Steam 6: Instruction Set Design and Architecture:
      • CLO11: Design and evaluate instruction set architectures (ISA) and microarchitectures, including concepts such as pipelining, superscalar execution, and out-of-order execution.

  By achieving these CLOs, students will gain a thorough understanding of the process from algorithm development to silicon implementation, equipping them with the skills necessary for careers in digital design and related fields.

  Some of the following tools that will be used in the Course (Steam Dependent):

  1. Algorithm Development:
  1. • Python
  2. Digital Design:
  1. • Verilog/SystemVerilog
  3. FPGA Design:
  1. • Xilinx Vivado
  4. ASIC Design and Simulation:
  1. • Cadence XCELIUM
     • Synopsys VCS
     • Mentor ModelSim
     • Mentor Questa
  5. Synthesis:
  1. • Cadence Genus
     • Synopsys Design Compiler
  6. Timing Analysis:
  1. • Cadence Tempus
     • Synopsys PrimeTime
  7. Physical Design and Layout:
  1. • Cadence Innovus
     • Synopsys IC Compiler
     • Calibre (DRC/LVS)
  8. Formal Verification:
  1. • Cadence Conformal
  9. Embedded Systems Programming:
  1. • Eclipse
     • Keil MDK
     • IAR Embedded Workbench
     • GCC
     • GDB
  10. Firmware Development:
  1. • Custom bootloader development environments