Sir Syed CASE Institute Of Technology

1. Fundamental Understanding:
   • CLO1: Demonstrate a comprehensive understanding of the digital design flow, including the challenges and techniques involved in mapping algorithms to silicon.
2. Algorithm Design and HW Mapping:
   • CLO2: Generate using GenAI code for realizing data structure algorithms, DSP algorithms, and machine learning algorithms (including CNNs) for efficient mapping in hardware.
3. Hardware Description Languages:
   • CLO3: Apply Verilog and SystemVerilog for RTL design and functional verification, demonstrating proficiency in generating code using Gen AI
4. Arithmetic and Computational Units:
   • CLO4: Generate code to implement basic arithmetic operations and computational units (e.g., addition, multiplication, MAC, trigonometric functions) in hardware.
5. Architecture Design:
   • CLO5: Design and evaluate different digital architectures (e.g., fully parallel, systolic, time-shared, micro-coded state machines) for specific computational tasks.
6. Practical Tool Usage:
   • CLO11: Utilize industry-standard tools such as Python, Verilog/SystemVerilog, FPGA logic synthesis tools, and Cadence tools (XCELIUM2003) for digital design and verification tasks.
7. Project Management and Collaboration:
   • CLO12: Work collaboratively on design projects, demonstrating project management skills and the ability to integrate and apply interdisciplinary knowledge.
8. Steam 1: Advanced Digital System Design:
   • CLO6: Create detailed RTL designs using advanced constructs and coding styles, implementing complex digital systems effectively.
9. Steam 2: Verification Techniques:
   • CLO7: Employ verification methodologies, including directed testing, random testing, and coverage-driven verification, using SystemVerilog and UVM.
10. Stream 3: Synthesis and Timing Analysis:
    • CLO8: Perform synthesis and timing analysis, optimizing designs for timing, area, and power, and conduct static timing analysis (STA).
11. Steam 4: Physical Design and Layout:
    • CLO9: Execute physical design tasks, including placement, routing, and compaction, adhering to design rules and constraints (DRC, LVS).
12. Stream 5: Embedded Systems Programming:
    • CLO10: Develop embedded software and drivers using programming languages (C, C++), real-time operating systems (RTOS), and firmware development tools.
13. Steam 6: Instruction Set Design and Architecture:
    • CLO11: Design and evaluate instruction set architectures (ISA) and microarchitectures, including concepts such as pipelining, superscalar execution, and out-of-order execution.

By achieving these CLOs, students will gain a thorough understanding of the process from algorithm development to silicon implementation, equipping them with the skills necessary for careers in digital design and related fields.

Some of the following tools that will be used in the Course (Steam Dependent):

1. Algorithm Development:

1. • Python

2. Digital Design:

1. • Verilog/SystemVerilog

3. FPGA Design:

1. • Xilinx Vivado

4. ASIC Design and Simulation:

1. • Cadence XCELIUM
   • Synopsys VCS
   • Mentor ModelSim
   • Mentor Questa

5. Synthesis:

1. • Cadence Genus
   • Synopsys Design Compiler

6. Timing Analysis:

1. • Cadence Tempus
   • Synopsys PrimeTime

7. Physical Design and Layout:

1. • Cadence Innovus
   • Synopsys IC Compiler
   • Calibre (DRC/LVS)

8. Formal Verification:

1. • Cadence Conformal

9. Embedded Systems Programming:

1. • Eclipse
   • Keil MDK
   • IAR Embedded Workbench
   • GCC
   • GDB

10. Firmware Development:

1. • Custom bootloader development environments