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Dr Anees Ullah       ( Assistant Professor )



Cell: 0      Email: anees.ullah@case.edu.pk



Educational Qualification:

Degree Specialization University Year
B.Sc Electrical Engineering UET Peshawar 2009
M.Sc Electrical Engineering UET Peshawar 2011
PHD Computer and Control Engineering Politecnico di Torino, ITALY 2015

                                                                                                                                                                                                                               


                                                                                                                                                                                                                               

Research Interest:

Title Description
Digital Design FPGA/ASICs design
Space Electronic Systems Radiation-hardened Design and Testing
Embedded Vision Systems Real-time Vision Systems, MPSoCs Implementation, Low-power FPGA Accelerators

                                                                                                                                                                                                                               


                                                                                                                                                                                                                               


                                                                                                                                                                                                                               


                                                                                                                                                                                                                               

Key Publications (Journals & Books):

S.No. Key Publications
1 Zhen Gao, Jinhua Zhu, Ruishi Han, Zhan Xu, Anees Ullah, Pedro Reviriego: Design and Implementation of Configuration Memory SEU Tolerant Viterbi Decoders in SRAM based FPGAs. IEEE Transactions on Nanotechnology 07/2019; PP(99):1-1., DOI:10.1109/TNANO.2019.2925872
2 Low delay Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes. Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Zhaochi Liu, Linzhe Li,Anees Ullah:. In Microelectronics Reliability 06/2019; 97(June 2019):31-37.,DOI:10.1016/j.microrel.2019.03.012
3 PR-TCAM: Ecient TCAM Emulation on Xilinx FPGAs Using Partial Recon guration. Pedro Reviriego, Anees Ullah, Salvatore Pontarelli:. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 03/2019; PP(99):1-5., DOI:10.1109/TVLSI.2019.2903980
4 Anees Ullah, Pedro Reviriego, Juan Antonio Maestro, "Multiple Cell Upsets Injection in BRAMs for Xilinx FPGAs", IEEE Transactions on device and materials reliability, Early Acces, 10.1109/TDMR.2018.2878806
5 Pedro Reviriego, Salvatore Pontarelli, Anees Ullah: Error Detection and Correction in SRAM Emulated TCAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2018; PP(99):1-5., DOI:10.1109/TVLSI.2018.2877131,
6 Anees Ullah, Pedro Reviriego, Juan Antonio Maestro, “An efficient methodology for on-chip SEU injection in flip-flops for Xilinx FPGAs”, IEEE Transactions in Nuclear Science, Vol 65, No. 4, April 2018
7 Anees Ullah, Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro: Majority Voting-based Reduced Precision Redundancy Adders. IEEE Transactions on Device and Materials Reliability 12/2017; PP(99):1-1., DOI:10.1109/TDMR.2017.2781186
8 Luis Andres Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer: A novel tool-flow for zero-overhead Cross-Domain Error resilient partially reconfigurable X-TMR for SRAM-based FPGAs. Journal of Systems Architecture 11/2017;, DOI:10.1016/j.sysarc.2017.10.009
9 Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro: Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. IEEE Transactions on Computers 08/2017; PP(99):1-1., DOI:10.1109/TC.2017.2737996
10 Anees Ullah, Ernesto Sanchez, Luca Sterpone, Luis Andrea Cardona, Carles Ferrer: An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. Microelectronics Reliability 06/2017; 75., DOI:10.1016/j.microrel.2017.06.032
11 Nasim Ullah, Anees Ullah, Asier Ibeas, Jorgea Herrerac: Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems. IEEE Access 05/2017; PP(99):1-1., DOI:10.1109/ACCESS.2017.2700439
12 Matteo Sonza Reorda, Luca Sterpone, Anees Ullah: An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Transactions on Computers 09/2016; PP(99):1-1., DOI:10.1109/TC.2016.2607749
13 Anees Ullah, Luca Sterpone: Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. Journal of Electronic Testing 08/2014; 30(4):425-442., DOI:10.1007/s10836-014-5463-7

                                                                                                                                                                                                                               

Key Publications (Conferences & Workshops):

S.No. Key Publications
1 Differential Based Area Ecient ROM-Less Quadrature Direct Digital Frequency Synthesis. Yasir Ali Khan,Anees Ullah, Hazrat Ali, Khawaja M. Yahya, Nazim Ali, Usman Karim Khan: . In 5th International Conference on Emerging Technologies; 12/2009, DOI:10.1109/ICET.2009.5353195
2 Phase compensated di erential based quadrature direct digital frequency synthesis Anees Ullah, Hazrat Ali, Yasir Ali Khan, Muhammad Aamir, Nazim Ali, Khawaja Muhammad Yahya: . In 2012 International Conference on Emerging Technologies, 10/2012, DOI: 10.1109/ICET.2012.6375485
3 An error-detection and selfrepairing method for dynamically and partially recon gurable systems Matteo Sonza Reorda, Luca Sterpone and Anees Ullah . In 2013 18th IEEE European Test Symposium (ETS); 05/2013, DOI:10.1109/ETS.2013.6569377
4 Dynamic neutron testing of Dynamically Recon gurable Processing Modules architecture Luca Sterpone, David Sabena,Anees Ullah,Mario Porrmann, Jens Hagemeyer, Jorgan Ilstad: . In Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on; 06/2013, DOI:10.1109/AHS.2013.6604220
5 On the optimal recon guration times for TMR circuits on SRAM based FPGAs. Luca Sterpone, and Anees Ullah . In Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on; 06/2013, DOI:10.1109/AHS.2013.6604220
6 E ective emulation of permanent faults in ASICs through dynamically recon gurable FPGAs Ernesto Sanchez, Luca Sterpone, and Anees Ullah . In 2014 24th International Conference on Field Programmable Logic and Applications (FPL), Sep 2014
7 Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays Pedro Reviriego, Salvatore Pontarelli, Anees Ullah, Ali Zahir. In IEEE International Conference on High Performance Switching and Routing 17-20 June 2018 Bucharest, Romania

                                                                                                                                                                                                                               
7/16/2019 3:51:00 PM