Login     Forgot Password  
Dr Anees Ullah       ( Assistant Professor )

Cell: 0      Email:

Educational Qualification:

Degree Specialization University Year
B.Sc Electrical Engineering UET Peshawar 2009
M.Sc Electrical Engineering UET Peshawar 2011
PHD Computer and Control Engineering Politecnico di Torino, ITALY 2015



Research Interest:

Title Description
Digital Design FPGA/ASICs design
Space Electronic Systems Radiation-hardened Design and Testing
Embedded Vision Systems Real-time Vision Systems, MPSoCs Implementation, Low-power FPGA Accelerators





Key Publications (Journals & Books):

S.No. Key Publications
1 Anees Ullah, Pedro Reviriego, Juan Antonio Maestro, "Multiple Cell Upsets Injection in BRAMs for Xilinx FPGAs", IEEE Transactions on device and materials reliability, Early Acces, 10.1109/TDMR.2018.2878806
2 Pedro Reviriego, Salvatore Pontarelli, Anees Ullah: Error Detection and Correction in SRAM Emulated TCAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2018; PP(99):1-5., DOI:10.1109/TVLSI.2018.2877131,
3 Anees Ullah, Pedro Reviriego, Juan Antonio Maestro, “An efficient methodology for on-chip SEU injection in flip-flops for Xilinx FPGAs”, IEEE Transactions in Nuclear Science, Vol 65, No. 4, April 2018
4 Anees Ullah, Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro: Majority Voting-based Reduced Precision Redundancy Adders. IEEE Transactions on Device and Materials Reliability 12/2017; PP(99):1-1., DOI:10.1109/TDMR.2017.2781186
5 Luis Andres Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer: A novel tool-flow for zero-overhead Cross-Domain Error resilient partially reconfigurable X-TMR for SRAM-based FPGAs. Journal of Systems Architecture 11/2017;, DOI:10.1016/j.sysarc.2017.10.009
6 Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro: Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. IEEE Transactions on Computers 08/2017; PP(99):1-1., DOI:10.1109/TC.2017.2737996
7 Anees Ullah, Ernesto Sanchez, Luca Sterpone, Luis Andrea Cardona, Carles Ferrer: An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. Microelectronics Reliability 06/2017; 75., DOI:10.1016/j.microrel.2017.06.032
8 Nasim Ullah, Anees Ullah, Asier Ibeas, Jorgea Herrerac: Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems. IEEE Access 05/2017; PP(99):1-1., DOI:10.1109/ACCESS.2017.2700439
9 Matteo Sonza Reorda, Luca Sterpone, Anees Ullah: An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Transactions on Computers 09/2016; PP(99):1-1., DOI:10.1109/TC.2016.2607749
10 Anees Ullah, Luca Sterpone: Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. Journal of Electronic Testing 08/2014; 30(4):425-442., DOI:10.1007/s10836-014-5463-7


1/17/2019 2:55:00 PM